1. Field of the Invention
The present invention relates to a multilayer chip capacitor that is suitable to be used as a decoupling capacitor in a power distribution network of a micro process unit (MPU), and more particularly, to a 2-terminal low-inductance chip capacitor that can achieve high equivalent series resistance (ESR) while minimizing an increase in equivalent series inductance (ESL).
2. Description of the Related Art
An operating frequency for a high-speed micro processor unit (MPU) is continuously increasing, leading to an increase in current consumption, and an operating voltage for an MPU chip is being lowered. Thus, it becomes more difficult to suppress noise of a DC supply voltage, which occurs due to sudden fluctuation of a load current of the MPU, below a certain level (generally, 5˜10%). To remove the voltage noise, a multilayer chip capacitor is being widely used in a power distribution network. The multilayer chip capacitor for decoupling removes the voltage noise by supplying a current to a central processing unit (CPU) at the time of sudden fluctuation of the load current.
Recently, the load current fluctuates even more rapidly with the further increase in operating frequency of the MPU. Therefore, a decoupling capacitor is required to have higher capacitance, higher equivalent series resistance (ESR) and lower equivalent series inductance (ESL), so that magnitude of an impedance of a power distribution network can be maintained at a low and constant level within a broad frequency band. This can ultimately contribute to suppressing the voltage noise caused by the sudden fluctuation of the load current.
A typical 2-terminal low inductance chip capacitor (LICC) being widely used these days is also called a reverse geometry capacitor (RGC). The LICC has an exterior and an internal electrode structure as illustrated in FIGS. 1A and 1B. Referring to FIGS. 1A and 1B, rectangular internal electrodes 1 and 2 having opposite polarities are alternately disposed in a capacitor body 21 of a related art LICC 20, with a dielectric layer 21a interposed therebetween. Because external electrodes 11 and 22 of the related art LICC 20 cover wide areas of longer side surfaces of the capacitor body 21, respectively, short current paths (as indicated by arrows in FIG. 1B) and large contact areas between the external electrodes 11 and 12 and the internal electrodes 1 and 2 can be achieved, thereby lowering the ESL. However, in this case, the ESR is also lowered as well as the ESL, because of the short current paths within the internal electrodes 1 and 2 and the large contact areas between the internal electrodes 1 and 2 and the external electrodes 11 and 12. The low ESR causes the power distribution network of the high-speed MPU to be unstable.